• The fetches binary coded instructions from memory, decodes the instructions into a series of simple actions and carries out these actions in a sequence of steps.
• The CPU also contains an address counter or instruction pointer register, which holds the address of the next instruction or data item to be fetched from memory.
• The address bus consists of 16, 20, 24 or 32 parallel signal lines.
• On these lines the CPU sends out the address of the memory location that is to be written to or read from.
• The no of memory location that the CPU can address is determined by the number of address lines.
• If the CPU has N address lines, then it can directly address 2N memory locations i.e. CPU with 16 address lines can address 216 or 65536 memory locations.
• The data bus consists of 8, 16 or 32 parallel signal lines.
• The data bus lines are bi-directional.
• This means that the CPU can read data in from memory or it can send data out to memory
• The control bus consists of 4 to 10 parallel signal lines.
• The CPU sends out signals on the control bus to enable the output of addressed memory devices or port devices.
• Typical control bus signals are Memory Read, Memory Write, I/O Read and I/O Write.
COMPONENTS OF CPU
Figure: Microprocessor Based System with Bus Architecture.
• The Microprocessor is divided